1. Field of the Invention
The present invention relates to a semiconductor memory apparatus called an SRAM.
2. Description of the Related Art
FIG. 1 shows the related art of a SRAM having a .times.4-bit arrangement. In this related art, a plurality of memory cells MC.sub.0, MC.sub.1, . . . are arranged in row and column directions to constitute a memory cell array MCA. Word lines W.sub.0, W.sub.1, . . . serving as output lines extending from a row address decoder RAD are used as the gate electrodes of a pair of transfer transistors in each of the memory cells MC.sub.0, MC.sub.1, . . . in each row.
A pair of true and complementary bit lines B.sub.0, B.sub.0 ', . . . are respectively connected to the pair of transfer transistors in each of the memory cells MC.sub.0, MC.sub.1, . . . in each column, and output lines extending from a column address decoder CAD are connected to column gates CG.sub.0, CG.sub.1, . . . of the pairs of bit lines B.sub.0, B.sub.0 ', . . . . The terminals of the pairs of bit lines B.sub.0, B.sub.0 ', . . . are connected to sense amplifiers SA.sub.0, SA.sub.1, . . . , and four sense amplifiers SA.sub.0 to SA.sub.3, . . . constituting a set are connected to input/output terminals I/O.sub.0 to I/O.sub.3, respectively.
Note that since the word lines W.sub.0, W.sub.1, . . . serve as the gate electrodes of the transfer transistors in the memory cells MC.sub.0, MC.sub.1, . . . as described above, the word lines W.sub.0, W.sub.1, . . . are formed by a first polysilicon layer on a semiconductor substrate. The bit lines , B.sub.0, B.sub.0 ', . . . generally consist of an Al-based alloy.
Although the speed performance of the SRAM is determined by several factors, a main factor is a time required for the charging/discharging operations of the bit lines B.sub.0, B.sub.0 ', . . . . In order to shorten this time, the capacitance and resistance of the bit lines B.sub.0, B.sub.0 ', . . . must be reduced.
For this purpose, the bit lines B.sub.0, B.sub.0 ', . . . are comprised of an Al-based alloy as described above to decrease the resistance. At the same time, as shown in FIG. 2, the thickness of an interlayer insulator 2 between the bit lines B.sub.0, B.sub.0 ', . . . and a polysilicon wiring layer 1 thereunder and the thickness of an interlayer insulator 4 between the bit lines B.sub.0, B.sub.0 ', . . . and a second Al wiring layer 3 thereon are increased as large as possible to decrease capacitances C.sub.1 and C.sub.2 of the bit lines B.sub.0, B.sub.0 ', . . . .
However, as the area of the memory cells MC.sub.0, MC.sub.1, . . . is reduced, the pitch of the bit lines B.sub.0, B.sub.0 ', . . . become small. For example, in a 4-Mbit SRAM, when a wiring width is set to be 0.8 .mu.m, and an interwiring space is set to be 0.8 .mu.m, the pitch is about 1.6 .mu.m. In a 16-Mbit SRAM, a wiring width and an interwiring space are reduced, and the pitch is decreased to about 1.1 .mu.m.
When the interwiring space is decreased, a capacitance C.sub.3 formed between the bit lines B.sub.0, B.sub.0 ', . . . which rarely poses a problem in a conventional technique cannot be neglected. In order to reduce the capacitance C.sub.3, only the thickness of the bit lines B.sub.0, B.sub.0 ', . . . needs to be reduced. However, the resistance of the bit lines B.sub.0, B.sub.0 ', . . . is increased by reducing the thickness of the bit lines B.sub.0, B.sub.0 ', . . . . Therefore, when the thickness of the bit lines B.sub.0, B.sub.0 ', . . . is reduced, the time required for the charging/discharging operations of the bit lines B.sub.0, B.sub.0 ', . . . cannot be shortened.
In each of the memory cells MC.sub.0, MC.sub.1, . . . , as shown in FIG. 3, spaces for contact holes 5 are required for the bit lines B.sub.0, B.sub.0 ',. . . . These spaces serve as one factor which determines the size of each of the memory cells MC.sub.0, MC.sub.1, . . . .
That is, when a minimum design rule is set to be F, and a processing margin is set to be f, the size of each of the memory cells MC.sub.0, MC.sub.1, . . . in a direction perpendicular to the extending direction of the bit lines B.sub.0, B.sub.0 ', . . . , i.e., the short sides direction of each of the memory cells MC.sub.0, MC.sub.1, . . . is defined as 4F +4f, and the size cannot be reduced to less than 4F+4f. In addition, in an Al wiring layer, the size F cannot be easily minimized because processing properties and reliability are degraded. This is an important factor which increases the size of each of the memory cells MC.sub.0, MC.sub.1, . . . .